1. Field of the Invention
The present invention relates to a method for evaluating a semiconductor device, in particular, relates to a method for evaluating a semiconductor device using a TEG (test element group, also refer to as test structure).
2. Description of the Related Art
Large scale integrated circuits typified by CPUs have been installed not only in computers but also in various kinds of electric appliances. In recent years, the large scale integrated circuits have been installed in cards and the like as well as the electronic appliances. Products including the large scale integrated circuits have been spread rapidly because of their convenience. Thus, it is thought that applications of the large scale integrated circuits will be continued to be expand.
Meanwhile, an integrated circuit can be obtained by arranging and connecting an enormous number of semiconductor elements such that a certain function can be obtained. However, when failures are caused, e.g., the integrated circuit does not work, since the integrated circuit includes too many semiconductor elements, it is very difficult to identify a cause of failures.
Therefore, in order to analyze the cause of failures of the integrated circuit, a TEG (test element group) is fabricated in each element to evaluate the respective elements (e.g., refer to patent document 1). [Patent Document 1]: Japanese Patent Application Laid-Open No. Hei 5-297077
However, it is difficult to statistically determine parameters by using one TEG Also, there are many parameters that adversely affect an integrated circuit. Therefore, in order to find out parameters that can operate an integrated circuit stably in designing the integrated circuit, enormous numbers of TEGs must be manufactured by way of trial and evaluated, thereby involving a lot of time and effort to produce.
Moreover, it is very difficult to separate an influence of variation caused by the difference of lots for manufacturing TEGs from an influence due to change of intended parameters.